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W9751G6IB
7.3
7.3.1
Command Function
Bank Activate Command
( CS = "L", RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 be row address)
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
t RCDmin specification, then additive latency must be programmed into the device to delay when the
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure t RCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been
activated it must be precharged before another Bank Activate command can be applied to the same
bank. The bank active and precharge times are defined as t RAS and t RP , respectively. The minimum
time interval between successive Bank Activate commands to the same bank is determined by the
RAS cycle time of the device (t RC ). The minimum time interval between Bank Activate commands is
t RRD .
Figure 12 — Bank activate command cycle: t RCD = 3, AL = 2, t RP = 3, t RRD = 2, t CCD = 2
7.3.2
Read Command
( CS = "L", RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
Address)
The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
Publication Release Date: Oct. 23, 2009
- 20 -
Revision A06
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